Clause 74 of IEEE Standard 802.3ap-2007 (the latest version is IEEE 802.3-2008) and IEEEP 802.3 D1.2 define a Forward Error Correction (FEC for short) sub-layer of a BASE-R physical layer applied to the 10 G Ethernet. This FEC sub-layer standard improves the BER rate of the system from 10−7 to 10−12 and this standard also descends to the 40 G/100 G Ethernet applications.
To be compatible with different Ethernet application layers, this protocol specifies that the FEC layer compresses the original frame header to set aside space for uploading FEC check bits, so that it is ensured this layer keeps the same frame length (Clause 74 of IEEE Standard 802.3ap-2007 defines a frame length of 2112 bits) as other application layers. However, such a processing method makes it quite difficult to identify the frame boundary between respective frames at the receiver side, and a large quantity of time is required for synchronization to the transmitter-side frames so as to find correct frame boundary positions.
FIG. 1 shows a universal circuit structure for frame synchronization as defined in Clause 74 of IEEE Standard 802.3ap-2007. A method used by this circuit structure comprises:
a) testing an assumed frame boundary position;
a1) descrambling received data by a PN-2112 generator starting from this assumed frame boundary position;
a2) performing an FEC check for data with the length of a frame starting from the assumptive frame boundary;
i) if the check does not match (i.e., the received check bit does not match the computed check bit), shifting the assumed frame boundary position by one bit position and repeating step a);
b) for an assumed frame boundary, confirming that the FEC check of each of n consecutive frames is correct;
b1) if the FEC check of any of the n consecutive frames is not correct, shifting the assumed frame boundary position by one bit position and re-starting the entire frame synchronization procedure;
b) if the FEC check of each of the n consecutive frames being received is correct, going to step c);
c) establishing frame synchronization;
d) if the FEC check of each of m consecutively received data frames is not correct, deeming frame synchronization as stepping out and re-starting the entire frame synchronization procedure.
For a frame length of 2112 bits, the above steps are repeated for at most 2111 times to traverse all of the possible 2112 positions to find a correct frame boundary position. Typically m=8 and n=4 in the above description.
In brief, frame synchronization logic needs to locate a correct frame boundary position in a frame such that the frame synchronization could be achieved. A defect in common method is that many frames are discarded so as to be adapted to the steps of one-bit shifting at a time, before finding a correct frame start position.
FIG. 2 schematically shows how to achieve frame synchronization by the common method. According to FIG. 2, the frame synchronization logic does not know the correct start position at the beginning, so it will assume a frame start position and check the assumed frame. But when the last bit of the first frame data is put into the frame synchronization logic, the frame synchronization logic cannot give a check result of this frame at once. This is because there is a delay caused by a pipeline structure-based design in the hardware implementation, which delay is caused by some function logic like scramble logic and is unavoidable. After this pipeline delay, if the frame synchronization logic detects that the position of the first frame boundary is not correct, the frame synchronization logic needs to assume the next frame boundary after shifting a subsequent assumptive frame boundary position by one bit. Due to the pipeline delay as shown in FIG. 2, there is no time to one-bit shift from the frame boundary of the second frame and proceed the checking for the second frame data at this moment. Hence, the frame synchronization logic has to discard all the second frame data. Then until the third frame data comes, the frame synchronization logic will make one-bit shifting based on the frame boundary of the third frame and repeat the check for the third frame as is done in the first frame.
So in the worst case, the frame synchronization logic will check 2112 frames, discard 2111 frames and perform 2111 one-bit shifts, which will take (2112+2111)*2112+2111=8,921,087 BT (bit time) to get the correct frame boundary (i.e. the frame's correct start bit). This synchronization time is much longer than other high-speed interfaces working on a close data rate (such as about 600,000 BT for SATA2.0 and about 500,000 BT for PCIE2.0).